A dark gap in a plated through-hole cross-section needs a location before it needs a diagnosis. Is copper missing on the barrel wall, at an inner-layer connection or near the hole entrance? The answer changes which process records the fabricator should review. PCB plating voids are local areas where the required metal coverage is absent or interrupted. They are not the same defect as a crack in otherwise deposited copper.
This article concerns bare-board plated holes. A solder void under a component and a void inside a filled via have different materials and inspection questions. Calling all three "via voids" can send an investigation to the wrong production line.
Table of Contents
A plated through hole has copper on its wall so that selected circuit layers can connect through the board. A plating void is a local break in that required metal coverage. The first report should describe what is actually visible: the hole identifier, affected layer or barrel location, length of the missing area in the observed section and whether copper remains on either side. "There is a void" is too broad for a root-cause decision.
Do not confuse the defect with a non-plated mounting hole. NPTH walls are intentionally left without a plated conductor. A blind via or buried via can also have a coverage defect, but it follows a different build sequence and needs its own sample plan. The hole type should come from the approved drill and stackup data, not from the appearance of one photograph.
Other terms require care. A barrel crack is a fracture in copper that had been deposited. A pullaway is a separation at an interface. A resin-fill cavity concerns the material inside a filled hole, not necessarily the copper on its wall. A solder void forms during assembly and is outside this bare-board discussion. One search result for "plating voids" may concern one of these other conditions, so the defect definition belongs at the start of the investigation.
Hole-wall metallization is part of the PTH route. This factory image shows the process area, not a microscopic plating void.
Trace the production order before changing a plating bath. Drilling establishes the hole wall. Cleaning and desmear prepare it. Activation and the first conductive deposit create a path for later copper electroplating. Subsequent steps can build more copper or, if the process is not controlled, remove or damage an earlier deposit. A void seen in the finished board may therefore have started before the final plating stage.
Resin smear over an inner copper edge can prevent the new metal from making the intended connection. Loose glass or resin debris may also obstruct a small area. Drilling damage is a possible contributor, but a rough wall by itself does not identify the cause of a particular void. The separate KnownPCB article on PCB hole wall roughness and plating risks explains why hole size and wall condition must be checked independently.
If the preparation was adequate, the team must still check the activation and initial deposition records. A local failure of solution contact, a bubble or a particle can leave an area without the conductive starting layer. Later electroplating does not automatically bridge every such gap. The University of Maryland's CALCE resin-smear note describes one interface mechanism, not every form of plating void.
Solution exchange, bath condition and current distribution affect where copper grows. A narrow, deep hole can make uniform deposition harder to maintain. Yet thin copper at the middle of a hole is not automatically a void; the cross-section must show what is missing and where. Metal that was initially present can also be lost or damaged in a later operation. The investigator should compare the observed shape with the route used for that production lot.
Industry practitioner Happy Holden discusses both failed initial coverage and later metal loss in his review of PTH hole-void mechanisms. It is a useful reason to investigate the complete process history rather than assign every void to electroplating.
Position and repetition narrow the investigation, but they do not prove a cause on their own. A single section may cut through a bubble-shaped gap, a particle or a damaged interface. A cluster of defects at similar positions across a panel is different evidence from one isolated hole. Record that distribution before adjusting settings.
| Observed location | Records to check first | Why the pattern is not a diagnosis |
|---|---|---|
| At an inner-layer junction | Drill condition, desmear, inner-layer preparation and activation | The gap may reflect interface preparation or a later metal problem. |
| On an isolated barrel-wall area | Particle control, wetting, bath entry and initial deposit | One section cannot show the full circumference of the hole. |
| Near the hole opening | Surface preparation and later imaging or handling steps | The missing metal may have been removed after the initial deposit. |
| Repeated across one panel area | Panel position, racking, solution movement and sampling map | A spatial trend still needs comparison with process evidence. |
The table is an investigation aid, not an IPC acceptance table. If engineering has a verified microsection of an actual void, add it here with the layer, cut direction and hole location. A photo of factory equipment must not be presented as defect evidence.
Final inspection helps identify boards for further review. The image is not a substitute for a labeled hole microsection.
A microsection can reveal the local barrel structure, copper coverage and inner-layer junction at the plane that was cut. It is destructive and location-specific. A clean section at one hole does not certify every plated hole in the lot. If a void is suspected, the sample plan should target the relevant hole type and the area where the pattern appeared.
Electrical testing checks whether the tested network meets its continuity and isolation conditions. It can expose an open circuit, but it does not show the shape of a small local copper gap. A board may pass an electrical test yet still require a microsection under its agreed inspection plan. Conversely, a failed electrical result does not identify which production step caused the failure. KnownPCB describes its broader PCB inspection and quality-management process separately.
A useful defect record contains the section image, hole and layer identifiers, the orientation of the cut, measured copper condition, sample source and lot identifier. Keep the raw observation separate from the proposed cause. If another sample contradicts the first, report both rather than selecting the picture that fits the initial theory.
Electrical testing verifies the tested circuit path. A microsection is needed to see the local copper structure inside a plated hole.
Do not copy a void percentage or a pass/fail sentence from a blog. First identify the product class, standard revision, customer drawing, hole type and required inspection method for this order. IPC's IPC-A-600 program description lists voids among the plated-through-hole conditions covered by printed-board acceptability criteria. The public page does not provide a universal limit that can replace the purchased standard and the customer's contract.
Separate three decisions. The inspector records what is visible. Engineering determines the likely process mechanism using additional evidence. Quality personnel apply the agreed acceptance criteria to the affected lot. Those decisions may happen in the same review, but a photograph alone cannot perform all three.
Before fabrication, provide Gerber or ODB++ files, NC drill data, stackup, finished board thickness and finished-hole requirements. Mark blind, buried and filled vias. State the required copper condition and test evidence where the design or order calls for them. These inputs let the fabricator identify narrow or deep holes that need closer review of the chosen metallization route. For design context rather than defect diagnosis, KnownPCB also discusses via geometry and plating distribution in high-current boards.
For a repeat defect, compare the affected hole map with drill-hit records, hole-preparation controls, activation and initial-deposit records, then later plating and handling data. A change should address the step supported by the evidence. If the next sample is clean, retain the earlier defect record as well so the team can tell whether the correction held across the rest of the panel or lot.
Request a plated-hole DFM and inspection review
No. A plating void is missing or interrupted metal in the fabricated board. A solder void is an empty area in a solder joint created during assembly. Their materials, production steps and inspection evidence differ.
No. Electrical testing checks circuit continuity and isolation under its test conditions. A microsection shows copper structure at the sampled cut. The order's inspection plan determines when each is needed.
No. The spot must be identified by location and material. Review drilling, hole preparation, initial deposition and later copper steps before assigning a process cause.
Happy Holden, Factors in PTH Reliability: Hole Voids, I-Connect007.
University of Maryland CALCE, Resin Smear.
IPC, IPC-A-600 Acceptability of Printed Boards program description.
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